Differential phase interpolator circuits are used in a variety of electronic systems where they serve to produce an output signal with a desired phase. Phase interpolators typically receive two input signals which have the same frequency and different phases. The phase interpolator uses these two input signals to produce an output signal which has a phase that lies somewhere between the phases of the two input signals. In this manner, a phase interpolator circuit produces an output signal with a desired phase that lies between the phases of its two input signals. A phase interpolator circuit, in general, is useful wherever phase adjustment of an output signal is required and reference signals are available. For example, phase interpolators may be used in a synchronous memory system to adjust the phase of an internal clock in a memory device to match the phase of an external system clock.
FIG. 1 illustrates a prior art differential phase interpolator circuit, also known as a phase mixer circuit. The circuit comprises two transistors M1 120 and M2 125 which are connected sharing their source nodes to form a differential transistor pair. The circuit further includes transistors M3 130 and M4 135 which are also connected as a differential pair. Two load resistors R1 150 and R2 160 are coupled to the drains of transistors M1 120 & M3 130 and M2 125 & M4 135, respectively. The circuit also includes two variable tail current sources I.sub.1 110 and I.sub.2 140, coupled to the sources of differential pairs M1/M2 120 125 and M3/M4 130, 135, respectively. The total current that is sunk by the two current sources, I.sub.1 110 and I.sub.2 140, is a fixed quantity I.sub.tot such that I.sub.1 +I.sub.2 =I.sub.tot and I.sub.tot *R.sub.1 =V.sub.s, where V.sub.s is the desired output voltage swing. Depending on the required phase of the output signal (i.e. the interpolation between the two input signals), this total current I.sub.tot will be distributed appropriately between I.sub.1 110 and I.sub.2 140. For example, the distribution could be I.sub.1 =0.3*I.sub.tot and I.sub.2 =0.7*I.sub.tot.
Under normal operation, the circuit receives two differential input signals, V.sub.in1 and V.sub.in2 that are applied to the inputs (i.e. gates) of the two differential pairs. The V.sub.in1 and V.sub.in2 signals have the same frequency but different phase. For example, V.sub.in2 may lag V.sub.in1 by 45 degrees. If all of the current is sunk through I.sub.1, i.e. I.sub.1 =I.sub.tot and I.sub.2 =0, only V.sub.in1 will contribute to the output signal. The resultant phase of the output signal will be determined only by the phase of V.sub.in1. The phase of the output signal determined under these conditions is designated as .O slashed..sub.1. Similarly, if all of the current is sunk through I.sub.2, i.e. I.sub.1 =0 and I.sub.2 =I.sub.tot, only V.sub.in2 will contribute to the output signal. In that instance, the phase of the output signal will be determined only by the phase of V.sub.in2. The phase of the output signal determined under these conditions is designated as .O slashed..sub.2. If V.sub.in2 lags V.sub.in1 by X degrees, then .O slashed..sub.2 -.O slashed..sub.1 =X degrees. If both current sources I.sub.1 110 and I.sub.2 140 are sinking some of the current, the output signal will be determined by both V.sub.in1 and V.sub.in2 Therefore, the phase of the resulting output signal will fall between .O slashed..sub.1 and .O slashed..sub.2. By properly distributing the total current between the two current sources I.sub.1 110 and I.sub.2 140, the output signal V.sub.out can be set to any phase between .O slashed..sub.1 and .O slashed..sub.2.
FIGS. 2A and 2B respectively illustrate input and output wave forms for the phase interpolator circuit under normal operating conditions. Output wave forms V.sub.out are shown for three interpolation conditions: V.sub.out (I.sub.1, I.sub.2)=V.sub.out (I.sub.tot, 0) 210; V.sub.out (I.sub.1, I.sub.2)=V.sub.out (0.5*I.sub.tot, 0.5*I.sub.tot)220; and V.sub.out (I.sub.1, I.sub.2)=V.sub.out (0, I.sub.tot)230. Under normal operating conditions, the phase interpolator circuit produces relatively smooth transitions on its output waveforms 210, 220, 230. As current is gradually switched from I.sub.1 110 to I.sub.2 140, the phase of the output signal gradually moves from .O slashed..sub.1 to .O slashed..sub.2. Maintaining a linear relationship between a change in current and a corresponding change in output phase is advantageous. An ideal, linear, monotonic phase interpolation transfer function is illustrated in FIG. 4.
Given that the two input signals maintain a fixed phase relationship regardless of the operating frequency, one of the most significant limitations of the phase interpolator circuit is that it only works effectively over a relatively small frequency range. Its operation is limited at both high and low frequencies.
The phase interpolator circuit has an upper limit to its operating frequency range because as the operating frequency is increased, the circuit eventually can not produce a full swing output signal. As the operating frequency is then further increased, the output signal amplitude continues to decrease, since I.sub.tot cannot be switched sufficiently fast to discharge the capacitance on the output nodes within half a cycle. In other words, the upper frequency limit of the circuit is primarily determined by the dominant RC pole at the output nodes.
One prior art solution to this high frequency limitation is to design the circuit with smaller resistors as Rand R2, while using a proportionately larger value of I.sub.tot This solution typically requires increasing the size of the transistors that make up the differential pairs. Additionally, while this solution solves the high frequency limitation, it limits circuit operation at lower frequencies. Therefore, although this design approach increases the upper frequency limit, it is not a good solution if the circuit needs to operate at low frequencies as well.
Additionally, increasing I.sub.tot increases the power used by the circuit, and increasing the size of the transistors increases the real estate required for the circuit. Additionally, at a certain point the output capacitance of the transistors dominates the other capacitances on the output nodes, and using a higher I.sub.tot and a correspondingly larger transistor does not extend the upper frequency limit. Thus, the high end of the operational frequency range of the phase interpolator circuit is limited by the value of R1 and R2, the value of I.sub.tot, the total capacitance on the output nodes of the circuit, the transconductance of the transistors, and, ultimately, the f.sub.T of the transistors. The value of f.sub.T is determined primarily by the transistor technology used to implement the circuit.
As the signal frequency is decreased, the phase interpolator circuit also eventually ceases to operate properly, but for a different reason. As the signal frequency is decreased, while maintaining a fixed phase relationship between the two input signals, the rise and fall times of both the input and output signals increasingly becomes a smaller fraction of a cycle. Additionally, the time between a V.sub.in1 voltage transition and a corresponding V.sub.in2 voltage transition increases. As this occurs, the output wave form begins to display a shelf-like kink half-way through its low-to-high and/or high-to-low voltage transitions when the circuit is interpolating between the two input signals, as illustrated in FIGS. 3A and 3B.
These kinks in the voltage transitions occur because the differential pairs in the circuit switch their tail currents too quickly. In other words, V.sub.in1 will make a full transition, thereby switching all of I.sub.1 's 110 current from M1 120 to M2 125 (or vice-versa) before V.sub.in2 begins its voltage transition. Because of the V.sub.in1 transition, the output signal will switch half-way. However, since V.sub.in2 has not yet begun its voltage transition, the output signal remains at this intermediate voltage until V.sub.in2 transitions. Only then will V.sub.out complete its voltage transition. This "half-switching effect" produces the shelf- like kink as illustrated in FIG. 3B when V.sub.out (I.sub.1, I.sub.2)=V.sub.out (0.5*I.sub.tot, 0.5*I.sub.tot). When the output signal displays a shelf-like kink, the circuit produces an undesirable, non-linear, S-shaped phase interpolation transfer function, as shown in FIG. 5. Such a transfer function is undesirable because there ceases to be a linear correlation between a change in I.sub.1 110, or I.sub.2 140, current and a resulting change in output phase. The output phase becomes too sensitive to small changes in I.sub.1 110 or I.sub.2 when the circuit is operating near I.sub.1 =0.5*I.sub.tot. Conversely, the output phase becomes too insensitive to small changes in the current of I.sub.1 110 or I.sub.2 when the circuit is operating near I.sub.1 =I.sub.tot or I.sub.1 =0. Additionally, the shelf-like transition makes the phase interpolator's output signal more susceptible to jitter, particularly when operating near I.sub.1 =I.sub.2 =0.5*I.sub.tot.